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6-Channel SMBus/I2C or PWM Dimming LED Driver with Phase Shift Control
ISL97671
The ISL97671 is a 6-Channel 45V dual dimming capable LED driver that can be used with either SMBus/I2C or PWM signal for dimming control. The ISL97671 drives 6 channels of LED to support 78 LEDs from 4.5V to 26V or 48 LEDs from a boost supply of 2.7V to 26V and a separate 5V bias on the ISL97671 VIN pin. The ISL97671 compensates for non-uniformity of the forward voltage drops in the LED strings with its 6 voltage controlled-current source channels. Its headroom control monitors the highest LED forward voltage string for output regulation, to minimize the voltage headroom and power loss in a typical multi-string operation. The ISL97671 features optional channel phase shift control to minimize the input, output ripple characteristics and load transients as well as spreading the light output to help reduce the video and audio interference from the backlight driver operation. The phase shift can be programmed with equal phase angle or adjustable in 7-bit resolution. The ISL97671 has a full range of dimming capabilities that include SMBus/I2C controlled PWM dimming or DC dimming. It can also do direct PWM dimming with as low as 350nS pulse on PWM pin which translates to a dutycycle of 0.007% at a 200Hz dimming frequency.
ISL97671
Features
* 6 Channels * 4.5V to 26.5V Input * 45V Output Max * Up to 40mA LED Current per channel * Extensive Dimming Control - PWM/DPST Dimming, I2C 8-bit with equal phase shift, and 0.007% Direct PWM dimming at 200Hz * Optional Master Fault Protection * PWM Dimming Linearity 0.4%~100% <30kHz * 600kHz/1.2MHz selectable switching frequency * Dynamic Headroom Control * Protections with Flag Indication - String Open/Short Circuit, VOUT Short Circuit, Overvoltage and Over-Temperature Protections - Optional Master Fault Protection * Current Matching 0.7% * 20 Ld 4mmx3mm QFN Package
Applications*(see page 27)
* Notebook Displays WLED or RGB LED Backlighting * LCD Monitor LED Backlighting * Automotive Displays LED Backlighting * Automotive or Traffic Lighting
Typical Application Circuit
VIN = 4.5~26.5V VOUT = 45V*, 40mA PER STRING
ISL97671 1 FAULT 2 VIN 4 VDC LX 20 OVP 16
PGND 19 7 SMBCLK/SCL 6 SMBDAT/SDA CH0 10 5 PWM 3 EN 17 RSET 8 FPWM 9 AGND CH1 11 CH2 12 CH3 13 CH4 14 CH5 15 COMP 18 *VIN > 12V
FIGURE 1. ISL97671 TYPICAL APPLICATION DIAGRAM WITH SMBus/I2C CONTROL
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL97671
VIN = 4.5~26.5V VOUT = 45V*, 40mA PER STRING
ISL97671 1 FAULT 2 VIN 4 VDC LX 20 OVP 16
PGND 19 7 SMBCLK/SCL 6 SMBDAT/SDA CH0 10 5 PWM 3 EN 17 RSET 8 FPWM 9 AGND CH1 11 CH2 12 CH3 13 CH4 14 CH5 15 COMP 18 *VIN > 12V
FIGURE 2. ISL97671 TYPICAL APPLICATION DIAGRAM WITH EXTERNAL PWM SIGNAL CONTROL
Block Diagram
45V*, 40mA PER STRING VIN = 4.5V TO 26.5V (6 x 13 = 78 EDs)
VIN EN
FAULT ISL97671
LX
VDC
REG FAULT/STATUS REGISTER OSC AND RAMP COMP =0 FET DRIVER
OVP
LOGIC
fPWM
LED PWM CONTROL
IMAX ILIMIT
PGND
CH0 COMP GM AMP REFERENCE GENERATOR HIGHEST VF STRING DETECT + OC, SC DETECT
CH5 *VIN > 12V
RSET AGND
+ -
OC, SC DETECT FAULT/STATUS REGISTER TEMP SENSOR
REGISTERS SMBCLK/SCL SMBDAT/SDA PWM SMBUS/I2C INTERFACE AND PWM CONTROl LOGIC PWM BRIGHTNESS CONTROL DEVICE CONTROL FAULT/STATUS IDENTIFICATION DC BRIGHTNESS CONTROL CONFIGURATION PWM/OC/SC DC
+ FAULT/STATUS REGISTER
FIGURE 3. ISL97671 BLOCK DIAGRAM
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Ordering Information
PART NUMBER (Notes 1, 2) ISL97671IRZ PART MARKING 7671 PACKAGE (Pb-free) 20 Ld 4x3 QFN PKG. DWG. # L20.3x4
Pin Configuration
ISL97671 (20 LD QFN) TOP VIEW
COMP 18 PGND RSET 17 16 OVP 15 CH5 14 CH4 13 CH3 12 CH2 11 CH1 7 SMBCLK/SCL* 8 FPWM 9 AGND 10 CH0 LX 20 FAULT VIN EN VDC PWM 1 2 3 4 5 SMBDAT/SDA* 6
ISL97671IRZ-EVAL Evaluation Board NOTES: 1. Add "-T" or "-TK" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL97671. For more information on MSL please see techbrief TB363.
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Pin Descriptions
PIN NAME FAULT VIN EN VDC PWM SMBDAT/SDA* SMBCLK/SCL* FPWM AGND CH0 CH1 CH2 CH3 CH4 CH5 OVP RSET COMP PGND LX PIN # TYPE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 O S I S I I/O I I S I I I I I I I I O S O
(I = Input, O = Output, S = Supply)
DESCRIPTION
Fault disconnect switch. Input voltage for the device and LED power. The device needs 4ms for initial power-up enable. It will be disabled if it is not biased for longer than 28ms. De-couple capacitor for internally generated supply rail. PWM brightness control pin or DPST control input. SMBus/I2C serial data input and output. When pins 6 and 7 are grounded or in logic 0's for longer than 60ms, the drivers will be controlled by external PWM signal. SMBus/I2C serial clock input. When pins 6 and 7 are grounded or in logic 0's for longer than 60ms, the drivers will be controlled by external PWM signal. Set PWM dimming frequency, FPWM by connecting a resistor. See the "PWM Dimming Frequency Adjustment" section for resistor calculation. Analog Ground for precision circuits. Input 0 to current source, FB, and monitoring. Input 1 to current source, FB, and monitoring. Input 2 to current source, FB, and monitoring. Input 3 to current source, FB, and monitoring. Input 4 to current source, FB, and monitoring. Input 5 to current source, FB, and monitoring. Overvoltage protection input. Resistor connection for setting LED current, (see Equation 2 for calculating the ILED(peak)). Boost compensation pin. Power ground Input to boost switch.
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Table of Contents
Typical Application Circuit ................................. 1 Block Diagram ................................................... 2 Pin Descriptions (I = Input, O = Output, S = Supply)..................................................... 3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . Thermal Information . . . . . . . . . . . . . . . . . . . . . Operating Conditions . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 5
Typical Performance Curves .............................. 8 Theory of Operation......................................... 10 PWM Boost Converter ...................................... 10 Enable ...........................................................10 OVP and VOUT Requirement .............................. 10 Current Matching and Current Accuracy ............. 11 Dynamic Headroom Control .............................. 11 Dimming Controls ........................................... 11 Maximum DC Current Setting . . . . . . . . . . . . . . . . . . 11 PWM Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 PWM Dimming Frequency Adjustment ................ 12 Phase Shift Control.......................................... 12 Switching Frequency........................................13 5V Low Dropout Regulator................................ 13 In-rush Control and Soft-start........................... 14 Fault Protection and Monitoring ......................... 14 Short Circuit Protection (SCP) ........................... 14 Open Circuit Protection (OCP) ........................... 14 Overvoltage Protection (OVP) ........................... 15 Undervoltage Lock-out ..................................... 15
Input Overcurrent Protection............................ 15 Over-Temperature Protection (OTP) .................. 15 SMBus/I2C Communications ................................ 18 Write Byte ......................................................... 18 Read Byte ......................................................... 18 Slave Device Address.......................................... 18 SMBus/I2C Register Definitions......................... 18 PWM Brightness Control Register (0x00)............ 20 Device Control Register (0x01)......................... 21 Fault/Status Register (0x02) ............................ 22 Identification Register (0x03) ........................... 22 DC Brightness Control Register (0x07) .............. 23 Configuration Register (0x08) .......................... 23 Output Channel Mask/Fault Readout Register (0x09) ............................................ 24 Phase Shift Control Register (0x0A) .................. 25 Components Selections ................................... 25 Input Capacitor .............................................. Inductor ........................................................ Output Capacitors........................................... Output Ripple................................................. Schottky Diode............................................... 25 25 26 26 26
Applications .................................................... 26 High Current Applications ................................ 26 Multiple Drivers Operation ............................... 27 16-Bit Dimming.............................................. 27 Revision History .............................................. 27 Products.......................................................... 27 Package Outline Drawing ................................ 28
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Absolute Maximum Ratings (TA = +25C)
VIN, EN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 28V FAULT . . . . . . . . . . . . . . . . . . . . . . . VIN-8.5V to VIN+0.3V VDC, COMP, RSET. . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V SMBCLK/SCL*, SMBDAT/SDA*, FPWM, PWM . . -0.3V to 5.5V EN, OVP . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.5V CH0 - CH5, LX . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V PGND, AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Above voltage ratings are all with respect to AGND pin ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . 3kV Machine Model (Tested per JESD22-A115-A) . . . . . . . 300V Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . 1kV
Thermal Information
Thermal Resistance (Typical) 20 Ld QFN Package (Notes 4, 5, 7). Thermal Characterization (Typical) JA (C/W) JC (C/W) 40 2.5 PSIJT (C/W)
20 Ld QFN Package (Note 6) . . . . . . . . . . . . 1 Maximum Continuous Junction Temperature . . . . . . +125C Storage Temperature . . . . . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . -40C to +85C
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 6. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die junction temperature can be estimated more accurately than the JC and JC thermal resistance ratings. 7. Refer to JESD51-7 high effective thermal conductivity board layout for proper via and plane designs.
Electrical Specifications
All specifications below are tested at TA = 25C; VIN = 12V, EN = 5V, RSET = 20.1k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. CONDITION MIN (Note 8) TYP MAX (Note 8) UNIT
PARAMETER GENERAL VIN (Note 9) IVIN_STBY VOUT
DESCRIPTION
Backlight Supply Voltage VIN Shutdown Current Output Voltage
13 LEDs per channel (3.2V/20mA type)
4.5
26.5 10
V A V V V V mV
4.5V < VIN 26V, FSW = 600kHz 8.55V < VIN 26V, FSW = 1.2MHz 4.5V < VIN 8.55V, FSW = 1.2MHz
45 45 VIN/0.19 2.6 275 3.3
VUVLO VUVLO_HYS REGULATOR VDC IVDC_STBY IVDC VLDO ENLow ENHi
Undervoltage Lockout Threshold Undervoltage Lockout Hysteresis
LDO Output Voltage Standby Current Active Current VDC LDO Droop Voltage Guaranteed Range for EN Input Low Voltage Guaranteed Range for EN Input High Voltage
VIN 6V EN = 0V EN = 5V VIN > 5.5V, 20mA
4.55
4.8
5 5
V A mA
5 20 200 0.5 1.8
mV V V
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Electrical Specifications
All specifications below are tested at TA = 25C; VIN = 12V, EN = 5V, RSET = 20.1k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) CONDITION MIN (Note 8) TYP 30.5 MAX (Note 8) UNIT ms
PARAMETER tENLow BOOST SWILimit rDS(ON) SS Eff_peak
DESCRIPTION EN Low Time Before Shut-down
Boost FET Current Limit Internal Boost Switch ON-resistance Soft-Start Peak Efficiency TA = +25C 100% LED Duty Cycle VIN = 12V, 72 LEDs, 20mA each, L = 10H with DCR 101m, TA = +25C VIN = 12V, 60 LEDs, 20mA each, L = 10H with DCR 101m, TA = +25C
1.5
2.0 235 7 92.9
2.7 300
A m ms %
90.8
%
IOUT/VIN DMAX
Line Regulation Boost Maximum Duty Cycle FSW = 1, 600kHz FSW = 0, 1.2MHz 90 81
0.1
% %
DMIN
Boost Minimum Duty Cycle
FSW = 1, 600kHz FSW = 0, 1.2MHz
9.5 17 475 0.97 600 1.14 640 1.31 10
%
fOSC_hi fOSC_lo ILX_leakage REFERENCE
Lx Frequency High Lx Frequency Low LX Leakage Current
FSW = 1, 600kHz FSW = 0, 1.2MHz LX = 45V, EN = 0V
kHz MHz A
FAULT DETECTION VSC Short Circuit Threshold Accuracy Reg0x08, SC[1:0] = 01 Reg0x08, SC[1:0] = 10 Reg0x08, SC[1:0]= 11 Temp_shtdw n Temp_Hyst VOVPlo OVPfault Temperature Shutdown Threshold Temperature Shutdown Hysteresis Overvoltage Limit on OVP Pin OVP Short Detection Fault Level 1.19 400 3.15 4.2 5.2 3.6 4.8 5.85 150 23 1.25 4.3 5.4 6.6 V V V C C V mV
CURRENT SOURCES IMATCH DC Channel-to-Channel Current Matching RSET = 20.1k, Reg0x00 = 0xFF, (IOUT = 20mA) -1.5 ILED = 20mA TA = +25C RSET = 20.1k VIN = 12V, VOUT = 45V, Fsw=1.2MHz, TA = +25C 1.2 500 1.22 40 1.24 0.7 1.0 %
IACC Vheadroom VRSET ILEDmax
Current Accuracy Dominant Channel Current Source Headroom at CH Pin Voltage at RSET Pin Maximum LED Current per Channel
+1.5
% mV mV mA
PWM GENERATOR Guaranteed Range for PWM Input Low Voltage Guaranteed Range for PWM Input High Voltage 1.5 0.8 VDD V V
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Electrical Specifications
All specifications below are tested at TA = 25C; VIN = 12V, EN = 5V, RSET = 20.1k, unless otherwise noted. Boldface limits apply over the operating temperature range, -40C to +85C. (Continued) CONDITION MIN (Note 8) TYP 200 8 Direct PWM Mode RFPWM = 660k 250 90 100 350 110 MAX (Note 8) 30,000 UNIT Hz bits ns Hz
PARAMETER FPWM PWMACC
DESCRIPTION PWM Input Frequency Range PWM Input Accuracy
tDIRECTPWM Direct PWM Minimum On Time FPWM FAULT PIN IFAULT VFAULT Fault Pull-down Current Fault Clamp Voltage with Respect to VIN PWM Dimming Frequency Range
VIN = 12V VIN = 12, VIN - VFAULT
12 6 1.3 1
21 7 1.4 3.5
30 8.3 1.5 5
A V V mA
LXstart_thres LX Start-up Threshold ILXStart-up SMBus/I2C VIL VIH VOL ILEAK SMBus/I2C tEN -SMB/I2C PWS fSMB tBUF tHD:STA LX Start-up Current INTERFACE Guaranteed Range for Data, Clock Input Low Voltage Guaranteed Range for Data, Clock Input High Voltage SMBus/I2C Data line Logic Low Voltage Input Leakage On SMBData/SMBClk TIMING SPECIFICATIONS (Note 10) Minimum Time Between EN high and SMBus/I2C Enabled Pulse Width Suppression on SMBCLK/SMBDAT SMBus/I2C Clock Frequency Bus Free Time Between Stop and Start Condition Hold Time After (Repeated) START Condition. After this Period, the First Clock is Generated Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock/data Fall Time Clock/data Rise Time 1F capacitor on VDC IPULLUP = 4mA Measured at 4.8V
0.8 1.5 VDD 0.17 -10 10
V V V A
2 0.15 0.45 400 1.3 0.6
ms s kHz s s
tSU:STA tSU:STO tHD:DAT tSU:DAT tLOW tHIGH tF tR NOTES:
0.6 0.6 300 100 1.3 0.6 300 300
s s ns ns s s ns ns
8. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 9. Independent from the numbers of LEDs, at minimum VIN of 4.5V, maximum VOUT is limited to 35V. And at maximum VIN of 26.5V, minimum VOUT is limited 28V. 10. Limits established by characterization and are not production tested.
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Typical Performance Curves
100 90 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 5 10 15 20 25 EFFICIENCY (%) 80 12VIN 24VIN 5VIN 100 90 80 70 60 50 40 30 20 10 0 0 5 10 15 20 ILED(mA) 25 30 35 12VIN 24VIN 5VIN 6P10S_30mA/CHANNEL
ILED(mA)
FIGURE 4. EFFICIENCY vs up to 20mA LED CURRENT (100% LED DUTY CYCLE) vs VIN
FIGURE 5. EFFICIENCY vs up to 30mA LED CURRENT (100% LED DUTY CYCLE) vs VIN
100 90 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0 5 10 15 VIN 20 25 30 EFFICIENCY (%) 80 580k 1.2MHz
100 80 60 40 20 0 0 580k 1.2MHz
5
10
15 VIN
20
25
30
FIGURE 6. EFFICIENCY vs VIN vs SWITCHING FREQUENCY AT 20mA (100% LED DUTY CYCLE)
100 80 EFFICIENCY (%) 70 +25C 60 50 40 30 20 10 0 0 5 10 15 VIN 20 25 30 +85C 0C -40C
FIGURE 7. EFFICIENCY vs VIN vs SWITCHING FREQUENCY AT 30mA (100% LED DUTY CYCLE)
0.40 CURRENT MATCHING(%) 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 -0.40 0 1 2 3 21 VIN 4 5 6 7 4.5 VIN
90
12 VIN
CHANNEL
FIGURE 8. EFFICIENCY vs VIN vs TEMPERATURE AT 20mA (100% LED DUTY CYCLE)
FIGURE 9. CHANNEL-TO-CHANNEL CURRENT MATCHING
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Typical Performance Curves
1.2 1.0 0.8 0.6 0.4 0.2 0
(Continued)
0.60 +25C VHEADROOM (V) 0.55 -40C
CURRENT
4.5 VIN 12 VIN
0.50
0C
0.45
0
1
2
3 DC
4
5
6
0.40 0
5
10
15 VIN (V)
20
25
30
FIGURE 10. CURRENT LINEARITY vs LOW LEVEL PWM DIMMING DUTY CYCLE vs VIN
FIGURE 11. VHEADROOM vs VIN AT 20mA
FIGURE 12. VOUT RIPPLE VOLTAGE, VIN = 12V, 6P12S AT 20mA/CHANNEL
FIGURE 13. IN-RUSH and LED CURRENT AT VIN = 6V FOR 6P12S AT 20mA/CHANNEL
FIGURE 14. IN-RUSH AND LED CURRENT AT VIN = 12V FOR 6P12S AT 20mA/CHANNEL
FIGURE 15. LINE REGULATION WITH VIN CHANGE FROM 6V TO 26V, VIN = 12V, 6P12S AT 20mA/CHANNEL
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Typical Performance Curves
(Continued)
FIGURE 16. LINE REGULATION WITH VIN CHANGE FROM 26V TO 6V FOR 6P12S AT 20mA/CHANNEL
FIGURE 17. LOAD REGULATION WITH ILED CHANGE FROM 0% TO 100% PWM DIMMING, VIN = 12V, 6P12S AT 20mA/CHANNEL
FIGURE 18. LOAD REGULATION WITH ILED CHANGE FROM 100% TO 0% PWM DIMMING, VIN = 12V, 6P12S AT 20mA/CHANNEL
FIGURE 19. ISL97671 SHUTS DOWN AND STOPS SWITCHING ~ 30ms AFTER EN GOES LOW
Theory of Operation
PWM Boost Converter
The current mode PWM boost converter produces the minimal voltage needed to enable the LED stack with the highest forward voltage drop to run at the programmed current. The ISL97671 employs current mode control boost architecture that has a fast current sense loop and a slow voltage feedback loop. Such architecture achieves a fast transient response that is essential for the notebook backlight application where the power can be a series of drained batteries or instantly change to an AC/DC adapter without rendering a noticeably visual nuisance. The number of LEDs that can be driven by ISL97671 depends on the type of LED chosen in the application. The ISL97671 is capable of boosting up to 45V and drive 6 channels of LEDs.
Enable
The EN pin is used to enable or disable the ISL97671 operation. It is a high voltage pin that can be tied directly to VIN up to 26.5V if the system lacks of I/O for enable signal.
OVP and VOUT Requirement
The Overvoltage Protection (OVP) pin has a function of setting the overvoltage trip level as well as limiting the VOUT regulation range. The ISL97671 OVP threshold is set by RUPPER and RLOWER as shown in Equation 1:
V OUT_OVP = 1.21V x ( R UPPER + R LOWER ) R LOWER (EQ. 1)
VOUT can only regulate between 64% and 100% of the VOUT_OVP such that: Allowable VOUT = 64% to 100% of VOUT_OVP
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For example, if 10 LEDs are used with the worst case VOUT of 35V. If R1 and R2 are chosen such that the OVP level is set at 40V, then the VOUT is allowed to operate between 25.6V and 40V. If the requirement is changed to a 6 LEDs 21V VOUT application, then the OVP level must be reduced and users should follow VOUT = (64% ~100%) OVP requirement. Otherwise, the headroom control will be disturbed such that the channel voltage can be much higher than expected and sometimes it can prevent the driver from operating properly. The ratio of the OVP capacitors should be the inverse of the OVP resistors. For example, if RUPPER/RLOWER = 33/1, then CUPPER/CLOWER = 1/33 with CUPPER = 100pF and CLOWER = 3.3nF. boost makes the output to the correct level such that the lowest channel pin is at the target headroom voltage. Since all LED stacks are connected to the same output voltage, the other channel pins will have a higher voltage, but the regulated current source circuit on each channel will ensure that each channel has the same programmed current. The output voltage will regulate cycle-by-cycle and is always referenced to the highest forward voltage string in the architecture.
Dimming Controls
The ISL97671 provides SMBus/I2C controlled PWM or DC dimming where the users need to turn the LEDs on through the SMBus/I2C communications (see the "SMBus/I2C Communications" section). On the other hand, the ISL97671 also provides PWM dimming by external PWM signal where the SMBCLK and SMBDAT pins need to pull low or grounded. The ISL97671 allows two ways of controlling the LED current, and therefore, the brightness. They are: 1. DC current adjustment 2. PWM chopping of the LED current defined in Step 1. There are various ways to achieve DC or PWM current control, which will be described in the following. MAXIMUM DC CURRENT SETTING The initial brightness should be set by choosing an appropriate value for RSET. This should be chosen to fix the maximum possible LED current:
401.8 I LEDmax = -------------R SET (EQ. 2)
Current Matching and Current Accuracy
Each channel of the LED current is regulated by the current source circuit, as shown in Figure 20. The LED peak current is set by translating the RSET current to the output with a scaling factor of 401.8/RSET. The source terminals of the current source MOSFETs are designed to run at 500mV to optimize power loss versus accuracy requirements. The sources of errors of the channel-to-channel current matching come from the op amps offset, internal layout, reference, and current source resistors. These parameters are optimized for current matching and absolute current accuracy. On the other hand, the absolute accuracy is additionally determined by the external RSET, and therefore, additional tolerance will be contributed by the current setting resistor. A 1% tolerance resistor is therefore recommended.
Once RSET is fixed, the LED DC current can be adjusted through Register 0x07 (BRTDC) as follows:
I LED = 1.58x ( BRTDC R SET ) (EQ. 3)
+ RSET
+ REF
BRTDC can be programmed from 0 to 255 in decimal and defaults to 255 (0xFF). If left at the default value, LED current will be fixed at ILEDmax. BRTDC can be adjusted dynamically on the fly during operation. BRTDC = 0 disconnects all channels. For example, if the maximum required LED current (ILED(max)) is 20mA, rearranging Equation 2 yields Equation 4:
R SET = 401.8 0.02 = 20.1k (EQ. 4)
+ PWM DIMMING DC DIMMING
If BRTDC is set to 200 then:
FIGURE 20. SIMPLIFIED CURRENT SOURCE CIRCUIT I LED = 1.58 * 200 20100 = 15.7mA (EQ. 5)
Dynamic Headroom Control
The ISL97671 features a proprietary Dynamic Headroom Control circuit that detects the highest forward voltage string or effectively the lowest voltage from any of the CH0-CH5 pins. When this lowest channel voltage is lower than the short circuit threshold, VSC, such voltage will be used as the feedback signal for the boost regulator. The
PWM CONTROL The ISL97671 provides three different PWM dimming methods, as described in the following. Each of these methods results in PWM chopping of the current in the LEDs for all 6channels to provide an average LED current. During the On periods, the LED current will be defined by the value of RSET and BRTDC, as described in
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Equations 2 and 3. The source of the PWM signal can be described as follows: 1. Internally generated 256 step duty cycle programmed through the SMBus/I2C. 2. External signal from PWM. 3. DPST mode. Internally generated signal with a duty cycle defined by the product of the external PWM and SMBus/I2C programmed PWM at the internal setting frequency. The default PWM dimming is in DPST mode. In all three methods, the average LED current of each channel is controlled by ILED and the PWM duty cycle in percent, as shown in Equation 6:
I LED ( ave ) = I LED x PWM (EQ. 6)
Where:
PWM DPST = BRT 255 x PWMI (EQ. 10)
Therefore:
I LED ( ave ) = I LED x BRT 255 x PWMI (EQ. 11)
Where BRT is the value held in Register 0x00 (default setting 0xFF) controlled by SMBus/I2C and PWM is the duty cycle of the incoming PWM signal. In this way, the users can change the PWM current in ratiometric manner to achieve DPST compliance backlight dimming. To use the DPST mode, users need to set Register 0x01 to 0x01 with external PWM signal. The DPST mode PWM frequency is adjusted by a resistor at the FPWM pin which will be described in "PWM Dimming Frequency Adjustment" on page 12. For example, if the SMBus/I2C controlled PWM duty is 80% dimming at 200Hz (see Equation 12) and the external PWM duty cycle is 60% dimming at 1kHz, the resultant PWM duty cycle is 48% dimming at 200Hz.
Method 1 (Internal Mode, SMBus/I2C controlled PWM) The average LED current of each channel is controlled by the internally generated PWM signal, as shown in Equation 7:
I LED ( ave ) = I LED x ( BRT 255 ) (EQ. 7)
PWM Dimming Frequency Adjustment
The PWM dimming frequency is set by an external resistor at the FPWM pin as:
6.66 x10 F PWM = ----------------------RFPWM
7
where BRT is the PWM brightness level programmed in the Register 0x00. BRT ranges from 0 to 255 in decimal and defaults to 255 (0xFF). BRT = 0 disconnects all channels. To use only the SMBus/I2C controlled PWM brightness control, users need to set Register 0x01 to 0x05 with EN/PWM in logic high. The SMBus/I2C controlled PWM frequency is adjusted by a resistor at the FPWM pin, which will be described in "PWM Dimming Frequency Adjustment" on page 12. Method 2 (External Mode) The average LED current of each channel can also be controlled by an external PWM signal, as shown in Equation 8:
LILED ( ave ) = I LED x PWMI
(EQ. 12)
where FPWM is the desirable PWM dimming frequency and RFPWM is the setting resistor. The PWM dimming frequency can be set or applied up to 30kHz with duty cycle from 0.4% to 100%.
Phase Shift Control
The ISL97671 is capable of delaying the phase of each current source to minimize load transients. By default, phase shifting is disabled as shown in Figure 21 where the channels PWM currents are switching uniformly. The duty cycles can be controlled by the data in PWM Brightness Control Register via the SMBus/I2C interface, an external PWM signal with the frequency set by the RFPWM, or by an external PWM signal with the frequency set by the incoming signal.
(EQ. 8)
The PWM dimming frequency can be set (see PWM Dimming Frequency Adjustment section) or applied up to 30kHz with duty cycles from 0.4% to 100%. The PWM dimming off time cannot be longer than 28ms or else the driver will enter shutdown. To use externally applied PWM signal only for brightness control, users need to set Register 0x01 to 0x03. Method 3 (DPST Mode) The average LED current of each channel can also be controlled by the product of the SMBus/I2C controlled PWM and the external PWM signals as:
I LED ( ave ) = I LED xPWM DPST (EQ. 9)
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tFPWM
PWMI
60%
tPWMin
40%
ILED0
tON
tOFF
ILED1 tON
tFPWM (tPWMout) tOFF
40% 60%
ILED1
ILED2
tD1 tD1 ILED3 tD1 ILED4
ILED2 ILED3
ILED4
ILED5
tD2 ILED1
FIGURE 21. NO DELAY (DEFAULT PHASE SHIFT DISABLED)
tD1 = Fixed Delay with Integer only while the decimal value will be discarded (eg. 63.75=63)
When EqualPhase = 1, the phase shift evenly spreads the channels switching across the PWM cycle, depending on how many channels are enabled, as shown in Figures 22 and 23. Equal phase means there are fixed delays between channels and such delay can be calculated as
t FPWM 255 t D1 = ------------------ x --------- 255 N t FPWM 255 t D2 = ------------------ x 255 - ( N - 1 ) --------- N 255 (EQ. 13)
FIGURE 23. 4 EQUAL PHASE CHANNELS PHASE SHIFT ILLUSTRATION
The ISL97671 allows the user to program the amount of phase shift degree in 7-bit resolution, as shown in Figure 24. To enable programmable phase shifting, the user must write to the Phase Shift Control register with EqualPhase = 0 and the desirable phase shift value of PhaseShift[6:0]. The delay between CH5 and the repeated CH0 is the rest of the PWM cycle.
tFPWM ILED0 tPD ILED1 tPD ILED2 tPD ILED3 tPD ILED4 tPD ILED5 tON tOFF
(EQ. 14)
where (255/N) is rounded down to the nearest integer. For example, if N = 6, (255/N) = 42, that leads to tD1 = tFPWM x 42/255 tD2 = tFPWM x 45/255 where tFPWM is the sum of tON and tOFF. N is the number of LED channels. The ISL97671 will detect the numbers of operating channels automatically.
PWMI
60%
40%
FIGURE 24. PHASE SHIFT WITH 7-BIT PROGRAMMABLE DELAY
60% 40%
ILED0 tD1 ILED1
Switching Frequency
tD1
ILED2 tD1 ILED3 tD1 ILED4 tD1 ILED5 tD2 ILED0 tON tFPWM tOFF
The default switching frequency is 600kHz but it can be selected to 600kHz or 1.2MHz if the SMBus/I2C communications is used. The switching frequency select bit is accessible in the SMBus/I2C Configuration Register 0x08 bit 2.
5V Low Dropout Regulator
A 5V LDO regulator is present at the VDC pin to develop the necessary low voltage supply, which is used by the chips internal control circuitry. Because VDC is an LDO pin, it requires a bypass capacitor of 1F or more for the regulation. Low input voltage also allows only lower output voltage applications only with the maximum boost ratio defined in "Components Selections" on page 25. The VDC pin can be used as a coarse reference with a few mA sourcing capability.
FIGURE 22. 6 EQUAL PHASE CHANNELS PHASE SHIFT ILLUSTRATION
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In-rush Control and Soft-start
The ISL97671 has separately built in independent in-rush control and soft-start functions. The in-rush control function is built around the short circuit protection FET, and is only available in applications, which include this device. At start-up, the fault protection FET is turned on slowly due to a 30A pull-down current output from the FAULT pin. This discharges the fault FET's gate-source capacitance, turning on the FET in a controlled fashion. As this happens, the output capacitor is charged slowly through the weakly turned on FET before it becomes fully enhanced. This results in a low in-rush current. This current can be further reduced by adding a capacitor (in the 1nF to 5nF range) across the gate-source terminals of the FET. Once the chip detects that the fault protection FET is turned on hard, it is assumed that in-rush has completed. At this point, the boost regulator will begin to switch and the current in the inductor will ramp-up. The current in the boost power switch is monitored and the switching is terminated in any cycle where the current exceeds the current limit. The ISL97671 includes a softstart feature where this current limit starts at a low value (275mA). This is stepped up to the final 2.2A current limit in 7 further steps of 275mA. These steps will happen over at least 8ms, and will be extended at low LED PWM frequencies if the LED duty cycle is low. This allows the output capacitor to be charged to the required value at a low current limit and prevents high input current for systems that have only a low to medium output current requirement. For systems with no master fault protection FET, the in-rush current will flow towards COUT when VIN is applied and it is determined by the ramp rate of VIN and the values of COUT and L. Due to the lag in boost response to any load change at its output, certain transient events (such as LED current steps or significant step changes in LED duty cycle) can transiently look like LED fault modes. The ISL97671 uses feedback from the LEDs to determine when it is in a stable operating region and prevents apparent faults during these transient events from allowing any of the LED stacks to fault out. See Table 1 for more details. A fault condition that results in an input current that exceeds the devices electrical limits will result in a shutdown of all output channels. The control device logic will remain functional such that the Fault/Status Register can be interrogated by the system. The root cause of the failure will be loaded to the volatile Fault/Status Register so that the host processor can interrogate the data for failure monitoring.
Short Circuit Protection (SCP)
The short circuit detection circuit monitors the voltage on each channel and disables faulty channels which are detected above the programmed short circuit threshold. There are three selectable levels of short circuit threshold (3.6V, 4.8V and 5.85V) that can be programmed through the Configuration Register 0x08 bits 0 and 1. When an LED becomes shorted, the action taken is described in Table 1. The default short circuit threshold is 5V. The detection of this failure mode can be disabled via Register 0x08, see Table 2B for additional information.
Open Circuit Protection (OCP)
When one of the LEDs becomes open circuit, it can behave as either an infinite resistance or a gradually increasing finite resistance. The ISL97671 monitors the current in each channel such that any string which reaches the intended output current is considered "good". Should the current subsequently fall below the target, the channel will be considered an "open circuit". Furthermore, should the boost output of the ISL97671 reaches the OVP limit or should the lower over-temperature threshold be reached, all channels which are not "good" will immediately be considered as "open circuit". Detection of an "open circuit" channel will result in a time-out before disabling of the affected channel. This time-out is sped up when the device is above the lower over-temperature threshold in an attempt to prevent the upper over-temperature trip point from being reached. Some users employ some special types of LEDs that have zener diode structure in parallel with the LED for ESD enhancement, thus enabling open circuit operation. When this type of LED goes open circuit, the effect is as if the LED forward voltage has increased, but no lighting. Any affected string will not be disabled, unless the failure results in the boost OVP limit being reached, allowing all other LEDs in the string to remain functional. Care should be taken in this case that the boost OVP limit and SCP limit are set properly, so as to make sure that multiple failures on one string do not cause all other good channels to be faulted out. This is due to the increased forward voltage of the faulty
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Fault Protection and Monitoring
The ISL97671 features extensive protection functions to cover all the perceivable failure conditions. The failure mode of a LED can be either open circuit or as a short. The behavior of an open circuited LED can additionally take the form of either infinite resistance or, for some LEDs, a zener diode, which is integrated into the device in parallel with the now opened LED. For basic LEDs (which do not have built-in zener diodes), an open circuit failure of an LED will only result in the loss of one channel of LEDs without affecting other channels. Similarly, a short circuit condition on a channel that results in that channel being turned off does not affect other channels unless a similar fault is occurring. All LED faults are reported via the SMBus/I2C interface to Register 0x02 (Fault/Status register). The controller is able to determine which channels have failed via Register 0x09 (Output Masking register). The controller can also choose to use Register 0x09 to disable faulty channels at start-up, resulting in only further faulty channels being reported by Register 0x02.
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ISL97671
channel making all other channel look as if they have LED shorts. See Table 1 for details for responses to fault conditions. Additionally, the ISL97671 monitors the voltage at the LX and OVP pins. At startup, a fixed current is injected out of the LX pins and into the output capacitor. The device will not start up unless the voltage at LX exceeds 1.2V. The OVP pin is also monitored such that if it rises above and subsequently falls below 20% of the target OVP level, the input protection FET will also be switched off.
Overvoltage Protection (OVP)
The integrated OVP circuit monitors the output voltage and keeps the voltage at a safe level. The OVP threshold is set as:
OVP = 1.21V x ( R UPPER + R LOWER ) R LOWER (EQ. 15)
Over-Temperature Protection (OTP)
The ISL97671 includes two over-temperature thresholds. The lower threshold is set to +130C. When this threshold is reached, any channel which is outputting current at a level significantly below the regulation target will be treated as "open circuit" and disabled after a timeout period. This time-out period is also reduced to 800s when it is above the lower threshold. The intention of the lower threshold is to allow bad channels to be isolated and disabled before they cause enough power dissipation (as a result of other channels having large voltages across them) to hit the upper temperature threshold. The upper threshold is set to +150C. Each time this is reached, the boost will stop switching and the output current sources will be switched off. Once the device has cooled to approximately +100C, the device will restart with the DC LED current level reduced to 75% of the initial setting. If the dissipation problem persists, subsequent hitting of the limit will cause identical behavior, with the current reduced in steps to 50% and finally 25%. Hitting of the upper threshold will also set the thermal fault bit of the Fault/Status register 0x02. Unless disabled via the EN pin, the device stays in an active state throughout, allows the external processor to interrogate the fault condition. For the extensive fault protection conditions, please refer to Figure 25 and Table 1 for details.
These resistors should be large to minimize the power loss. For example, a 1Mk RUPPER and 30k RLOWER sets OVP to 41.2V. Large OVP resistors also allow COUT discharges slowly during the PWM Off time. Parallel capacitors should also be placed across the OVP resistors such that RUPPER/RLOWER = CLOWER/CUPPER. Using a CUPPER value of at least 30pF is recommended. These capacitors reduce the AC impedance of the OVP node, which is important when using high value resistors.
Undervoltage Lock-out
If the input voltage falls below the UVLO level of 2.45V, the device will stop switching and be reset. Operation will restart only if the device is re-enabled through SMBus/I2C interface once the input voltage is back in the normal VIN and operating range. In non-SMBus/I2C applications, the part will automatically restart once the input voltage clears the UVLO threshold with the part already enabled.
Input Overcurrent Protection
During normal switching operation, the current through the internal boost power FET is monitored. If the current exceeds the current limit, the internal switch will be turned off. This monitoring happens on a cycle by cycle basis in a self protecting way.
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VIN LX VOUT
DRIVER
FAULT
LX O/P SHORT OVP
IMAX
ILIMIT
LOGIC
FET DRIVER
VSC
CH0
VSET/2 REG
CH5
THRM SHDN
REF T2 TEMP SENSOR T1 VSET + Q0 VSET + PWM/OC5/SC5 Q5
OTP
PWM/OC0/SC0 FAULT/ STATUS REGISTER SMBUS/I2C CONTROL LOGIC
DC CURRENT
FIGURE 25. SIMPLIFIED FAULT PROTECTIONS TABLE 1. PROTECTIONS TABLE VOUT REGULATED BY Highest VF of CH1 through CH5
CASE 1
FAILURE MODE CH0 Short Circuit
DETECTION MODE
FAILED CHANNEL ACTION
GOOD CHANNELS ACTION CH1 through CH5 Normal
CH0 ON and burns power. Upper Over-Temperature Protection limit (OTP) not triggered and CH0 < 4V Upper OTP triggered but VCH0 < 4V
2
CH0 Short Circuit
All channels go off until chip Same as CH0 cooled and then comes back on with current reduced to 76%. Subsequent OTP triggers will reduce IOUT further. CH1 disabled after 6 PWM cycle CH1 through CH5 Normal time-out. VOUT will ramp to OVP. CH1 will time-out after 6 PWM cycles and switch off. VOUT will drop to normal level. CH1 remains ON and has highest VF, thus VOUT increases. CH1 through CH5 Normal
Highest VF of CH1 through CH5
3
CH0 Short Circuit
Upper OTP not triggered but CH0 > 4V Upper OTP not triggered and CH0 < 4V Upper OTP not triggered and CH0 < 4V Upper OTP triggered but CH0 < 4V
Highest VF of CH1 through CH5 Highest VF of CH1 through CH5 VF of CH0
4
CH0 Open Circuit with infinite resistance CH0 LED Open Circuit but has paralleled Zener CH0 LED Open Circuit but has paralleled Zener
5
CH1 through CH5 ON, Q1 through Q5 burn power
6
All channels go off until chip Same as CH0 cooled and then comes back on with current reduced to 76%. Subsequent OTP triggers will reduce IOUT further
VF of CH0
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TABLE 1. PROTECTIONS TABLE (Continued) VOUT REGULATED BY VF of CH0
CASE 7
FAILURE MODE CH0 LED Open Circuit but has paralleled Zener
DETECTION MODE Upper OTP not triggered but CHx > 4V
FAILED CHANNEL ACTION CH0 remains ON and has highest VF, thus VOUT increases.
GOOD CHANNELS ACTION VOUT increases, then CH-X switches OFF after 6 PWM cycles. This is an unwanted shut off and can be prevented by setting OVP at an appropriate level.
8
Channel-toChannel VF too high Channel-toChannel VF too high Output LED stack voltage too high VOUT/LX shorted to GND at start-up or VOUT shorted in operation
Lower OTP triggered but CHx < 4V Upper OTP triggered but CHx < 4V VOUT > VOVP
Any channel at below the target current will fault out after 6 PWM cycles. Remaining channels driven with normal current. All channels go off until chip cooled and then comes back on with current reduced to 76%. Subsequent OTP triggers will reduce IOUT further Any channel that is below the target current will time-out after 6 PWM cycles, and VOUT will return to the normal regulation voltage required for other channels.
Highest VF of CH0 through CH5 Highest VF of CH0 through CH5 Highest VF of CH0 through CH5
9
10
11
LX current and timing The chip is permanently shutdown 31mS after power-up if VOUT/Lx is shorted to GND. are monitored. OVP pins monitored for excursions below 20% of OVP threshold.
SMBCLK VIH VIL
tLOW
tR
tF
tHD:STA SMBDAT VIH VIL tBUF
tHD:DAT
tHIGH tSU:DAT
tSU:STA
tSU:STO
P
S
S
P
NOTES: SMBus/I2C Description S = start condition P = stop condition A = acknowledge A = not acknowledge R/W = read enable at high; write enable at low
FIGURE 26. SMBUS/I2C INTERFACE
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1 S
7 Slave Address Master to Slave Slave to Master
1 W
1 A
8 Command Code
1 A
8 Data byte
1 A
1 P
FIGURE 27. WRITE BYTE PROTOCOL
1 S
7 Slave Address
1 W
1 A
8 Command Code
1 A
1 S
8 Slave Address
1 R
1 A
8 Data Byte
1 A
1 P
Master to Slave Slave to Master
FIGURE 28. READ BYTE PROTOCOL
SMBus/I2C Communications
The ISL97671 can be controlled by SMBus/I2C for PWM or DC dimming. The LEDs driving is default to off and the users will need the SMBus/I2C interface to enable the driving and controlling of various parameters that will be described in this section. Please note that the ISL97671 can also be controlled by an external PWM signal for PWM dimming without any SMBus/I2C interface. To do so, the users need to pull the SMBCLK and SMBDAT pins to low or ground the pins permanently if SMBus/I2C control is not used. The switching frequency is fixed at 600kHz if SMBus/I2C is not used.
shaded label that is used on cycles during which the slaved backlight controller "owns" or "drives" the Data line. All other cycles are driven by the "host master."
Slave Device Address
The slave address contains 7 MSB plus one LSB as R/W bit, but these 8 bits are usually called Slave Address bytes. As shown in Figure 29, the high nibble of the Slave Address byte is 0x5 or 0101b to denote the "backlight controller class." Bit 3 in the lower nibble of the Slave Address byte is 1. Bit 0 is always the R/W bit, as specified by the SMBus/I2C protocol. Note: In this document, the device address will always be expressed as a full 8-bit address instead of the shorter 7-bit address typically used in other backlight controller specifications to avoid confusion. Therefore, if the device is in the write mode where bit 0 is 0, the slave address byte is 0x58 or 01011000b. If the device is in the read mode where bit 0 is 1, the slave address byte is 0x59 or 01011001b. The backlight controller may sense the state of the pins at POR or during normal operation - the pins will not change state while the device is in operation.
Write Byte
The Write Byte protocol is only three bytes long. The first byte starts with the slave address followed by the "command code," which translates to the "register index" being written. The third byte contains the data byte that must be written into the register selected by the "command code". A shaded label is used on cycles during which the slaved backlight controller "owns" or "drives" the Data line. All other cycles are driven by the "host master."
Read Byte
As shown in Figure 28, the four byte long Read Byte protocol starts out with the slave address followed by the "command code" which translates to the "register index." Subsequently, the bus direction turns around with the re-broadcast of the slave address with bit 0 indicating a read ("R") cycle. The fourth byte contains the data being returned by the backlight controller. That byte value in the data byte reflects the value of the register being queried at the "command code" index. Note the bus directions, which are highlighted by the 18
SMBus/I2C Register Definitions
The backlight controller registers are Byte wide and accessible via the SMBus/I2C Read/Write Byte protocols. Their bit assignments are provided in the following sections with reserved bits containing a default value of "0".
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MSB LSB
0
1
0
1
1
0
0
R/W
FIGURE 29. SLAVE ADDRESS BYTE DEFINITION TABLE 2A. ISL97671 REGISTER LISTING
ADDRESS 0x00 REGISTER PWM Brightness Control Register Device Control Register Fault/Status Register Identification Register DC Brightness Control Register BIT 7 BRT7 BIT 6 BRT6 BIT 5 BRT5 BIT 4 BRT4 BIT 3 BRT3 BIT 2 BRT2 BIT 1 BRT1 BIT 0 BRT0 DEFAULT SMBUS/I2C VALUE PROTOCOL 0xFF Read and Write
0x01
Reserved
Reserved
RE AD /W RI TE
DEVICE IDENTIFIER
DEVICE ADDRESS
Reserved
BI T
Reserved Reserved PWM_MD
PWM_SEL
BL_CTL
0x00
Read and Write Read Only Read Only Read and Write Read and Write Read and Write Read and Write
0x02 0x03 0x07
Reserved LED PANEL BRTDC7
Reserved MFG3 BRTDC6
2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN MFG2 BRTDC5 MFG1 BRTDC4 MFG0 BRTDC3 REV2 BRTDC2 REV1 BRTDC1
FAULT REV0 BRTDC0
0x00 0xC8 0xFF
0x08 0x09
Configuration Reserved DirectPWM Register Output Channel Register Phase Shift Deg Reserved Reserved
0 CH5
1 CH4
1 CH3
FSW CH2
VSC1 CH1
VSC0 CH0
0x1F 0x3F
0x0A
Equal Phase
Phase Shift6
Phase Shift5
Phase Shift4
Phase Shift3
Phase Shift2
Phase Shift1
Phase Shift0
0x00
TABLE 2B. DATA BIT DESCRIPTIONS ADDRESS 0x00 0x01 REGISTER PWM Brightness Control Register Device Control Register DATA BIT DESCRIPTIONS BRT[7..0] = 256 steps of DPWM duty cycle brightness control PWM_MD = PWM mode select bit (1 = absolute brightness, 0 = % change), default = 0 PWM_SEL = Brightness control select bit (1 = control by PWMI, 0 = control by SMBus/I2C), default = 0 BL_CTL = BL On/Off (1 = On, 0 = Off), default = 0 2_CH_SD = Two LED output channels are shutdown (1 = shutdown, 0 = OK) 1_CH_SD = One LED output channel is shutdown (1 = shutdown, 0 = OK) BL_STAT = BL status (1 = BL On, 0 = BL Off) OV_CURR = Input overcurrent (1 = Overcurrent condition, 0 = Current OK) THRM_SHDN = Thermal Shutdown (1 = Thermal fault, 0 = Thermal OK) FAULT = Fault occurred (Logic "OR" of all of the fault conditions) MFG[3..0] = Manufacturer ID (16 vendors available. Intersil is vendor ID 9) REV[2..0] = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins)
0x02
Fault/Status Register
0x03
Identification Register
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TABLE 2B. DATA BIT DESCRIPTIONS (Continued) ADDRESS 0x07 0x08 REGISTER DC Brightness Control Register Configuration Register DATA BIT DESCRIPTIONS BRTDC[7..0] = 256 steps of DC brightness control DirectPWM = Forces the PWM input signal to directly control the current sources. Bits 3, 4, and 5 should be 1, 1, 0 FSW = Switching frequencies selection, FSW = 0 = 1.2MHz. FSW = 1 = 600kMHz VSC[1..0] = Short circuit thresholds selection, 0 = disabled, 1 = 3.6V, 2 = 4.8V, 3 = 5.85V CH[5..0] = Output Channel Read and Write. In Write, 1 = Channel Enabled, 0 = Channel Disabled. In Read, 1 = Channel OK, 0 = Channel Not OK/Channel disabled EqualPhase = Controls phase shift mode - When 1, phase shift is 360/N (where N is the number of channels enabled). When 0, phase shift is defined by PhaseShift<6:0>. PS[6..0] = 7-bit Phase shift setting - phase shift between each channel is PhaseShift<6:0>/(255*PWMFreq). In direct PWM modes, phase shift between each channel is PhaseShift<6:0>/12.8MHz.
0x09 0x0A
Output Channel Mask/Fault Readout Register Phase Shift Degree
PWM Brightness Control Register (0x00)
The Brightness control resolution has 256 steps of PWM duty cycle adjustment. The bit assignment is shown in Figure 30. All of the bits in this Brightness Control Register can be read or write. Step 0 corresponds to the minimum step where the current is less than 10A. Steps 1 to 255 represent the linear steps between 0.39% and 100% duty cycle with approximately 0.39% duty cycle adjustment per step. * An SMBus/I2C Write Byte cycle to Register 0x00 sets the PWM brightness level only if the backlight controller is in SMBus/I2C mode (see Table 3)
REGISTER 0x00 BRT7 BRT6 PWM BRIGHTNESS CONTROL REGISTER BRT5 BRT4 BRT3
Operating Modes selected by Device Control Register Bits 1 and 2). * An SMBus/I2C Read Byte cycle to Register 0x00 returns the programmed PWM brightness level. * An SMBus/I2C setting of 0xFF for Register 0x00 sets the backlight controller to the maximum brightness. * An SMBus/I2C setting of 0x00 for Register 0x00 sets the backlight controller to the minimum brightness output. * Default value for Register 0x00 is 0xFF.
BRT2
BRT1
BRT0
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT BRT[7..0] BIT FIELD DEFINITIONS = 256 steps of PWM brightness levels
FIGURE 30. DESCRIPTIONS OF BRIGHTNESS CONTROL REGISTER
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REGISTER 0x01 RESERVE D RESERVE D DEVICE CONTROL REGISTER RESERVE D RESERVE D RESERVE D
PWM_MD PWM_SEL
BL_CTL
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) PWM_MD X 0 0 1 1 PWM_SEL X 0 1 0 1 BL_CTL 0 1 1 1 1 Backlight Off SMBus/I2C and PWM dimming (DPST) PWMI controlled PWM dimming SMBus/I2C controlled PWM dimming SMBus/I2C controlled PWM dimming MODE
FIGURE 31. DESCRIPTIONS OF DEVICE CONTROL REGISTER
Device Control Register (0x01)
This register has two bits that control either SMBus/I2C controlled or external PWM controlled PWM dimming and a single bit that controls the BL ON/OFF state. The remaining bits are reserved. The bit assignment is shown in Figure 31. All other bits in the Device Control Register will read as low unless otherwise written. * All reserved bits have no functional effect when written. * All defined control bits return their current, latched value when read. A value of 1 written to BL_CTL turns on the BL in 4ms or less after the write cycle completes. The BL is * deemed to be on when Bit 3 BL_STAT of Register 0x02 is 1 and Register 0x09 is not 0. * A value of 0 written to BL_CTL immediately turns off the BL. The BL is deemed to be off when Bit 3 BL_STAT of Register 0x02 is 0 and Register 0x09 is 0. * When mode with DPST is selected, Register 0x00 reflects the last value written to it from SMBus/I2C. The default value for Register 0x01 is 0x00.
TABLE 3. OPERATING MODES SELECTED BY DEVICE CONTROL REGISTER BITS 1 AND 2 PWM_MD PWM_SEL X 1 0 1 0 0 PWM Mode SMBus/I2C Mode SMBus/I2C and PWM Mode with DPST MODE
The PWM_SEL bit determines whether the SMBus/I2C or PWM input should drive the output brightness in terms of PWM dimming. When PWM_SEL bit is 1, the PWM drives the output brightness regardless of what the PWM_MD is. When the PWM_SEL bit is 0, the PWM_MD bit selects the manner in which the PWM dimming is to be interpreted; when this bit is 1, the PWM dimming is based on the SMBus/I2C brightness setting. When this bit is 0, the PWM dimming reflects a percentage change in the current brightness programmed in the SMBus/I2C Register 0x00, i.e. DPST (Display Power Saving Technology) mode as:
DSPT Brightness = Cbt x PWM (EQ. 16)
Where: Cbt = Current brightness setting from SMBus/I2C Register 0x00 without influence from the PWM PWM = is the percent duty cycle of the PWM For example, the Cbt = 50% duty cycle programmed in the SMBus/I2C Register 0x00 and the PWM frequency is tuned to be 200Hz with an appropriate capacitor at the FPWM pin. On the other hand, PWM is fed with a 1kHz 30% high PWM signal. When PWM_SEL = 0 and PWM_MD = 0, the device is in DPST operation where DPST brightness = 15% PWM dimming at 200Hz.
SMBus/I2C
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Fault/Status Register (0x02)
This register has 6 status bits that allow monitoring of the backlight controller's operating state. Bit 0 is a logical "OR" of all fault codes to simplify error detection. Not all of the bits in this register are fault related (Bit 3 is a simple BL status indicator). The remaining bits are reserved and return a "0" when read and ignore the bit value when written. All of the bits in this register are read-only, with the exception of bit 0, which can be cleared by writing to it. * A Read Byte cycle to Register 0x02 indicates the current BL on/off status in BL_STAT (1 if the BL is on, 0 if the BL is off). * A Read Byte cycles to Register 0x2 also returns FAULT as the logical OR of THRM_SHDN, OV_CURR, 2_CH_SD, and 1_CH_SD should these events occur. * 1_CH_SD returns a 1 if one or more channels have faulted out. * 2_CH_SD returns a 1 if two or more channels have faulted out. * A fault will not be reported in the event that the BL is commanded on and then immediately off by the system. * When FAULT is set to 1, it will remain at 1 even if the signal which sets it goes away. FAULT will be cleared when the BL_CTL bit of the Device Control Register is toggled or when written low. At that time, if the fault condition is still present or reoccurs, FAULT will be set to 1 again. BL_STAT will not cause FAULT to be set. * The default value for Register 0x02 is 0x00.
Identification Register (0x03)
The ID register contains 3 bit fields to denote the LED driver (always set to 1), manufacturer and the silicon revision of the controller IC. The bit field widths allow up to 16 vendors with up to 8 silicon revisions each. In order to keep the number of silicon revisions low, the revision field will not be updated unless the part will make it out to the user's factory. Thus, if during the engineering development process, 3 silicon spins were needed, the next available revision ID would be used for all 3 spins until that same ID made it to the factory. Except Bit 7, which has to be 1, all of the bits in this register are readonly. * Vendor ID 9 represents Intersil Corporation. * The default value for Register 0x03 is 0xC8. The initial value of REV shall be 0. Subsequent values of REV will increment by 1.
REGISTER 0x02
FAULT/STATUS REGISTER FAULT Bit 0 (R)
RESERVED RESERVED 2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN Bit 7 (R) BIT Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 6 (R) Bit 5 (R) Bit 4 (R) Bit 3 (R) Bit 2 (R) Bit 1 (R)
BIT ASSIGNMENT 2_CH_SD 1_CH_SD BL_STAT OV_CURR THRM_SHDN FAULT
BIT FIELD DEFINITIONS = Two LED output channels are shutdown (1 = shutdown, 0 = OK) = One LED output channel is shutdown (1 = shutdown, 0 = OK) = BL Status (1 = BL On, 0 = BL Off) = Input Overcurrent (1 = Overcurrent condition, 0 = Current OK) = Thermal Shutdown (1 = Thermal Fault, 0 = Thermal OK) = Fault occurred (Logic "OR" of all of the fault conditions)
FIGURE 32. DESCRIPTIONS OF FAULT/STATUS REGISTER
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REGISTER 0x03 LED PANEL Bit 7 = 1 ID REGISTER
MFG3 Bit 6 (R)
MFG2 Bit 5 (R)
MFG1 Bit 4 (R)
MFG0 Bit 3 (R)
REV2 Bit 2 (R)
REV1 Bit 1 (R)
REV0 Bit 0 (R)
BIT ASSIGNMENT MFG[3..0]
BIT FIELD DEFINITIONS = Manufacturer ID. See "Identification Register (0x03)" on page 22. data 0 to 8 in decimal correspond to other vendors data 9 in decimal represents Intersil ID data 10 to 14 in decimal are reserved data 15 in decimal Manufacturer ID is not implemented = Silicon rev (Rev 0 through Rev 7 allowed for silicon spins) FIGURE 33. DESCRIPTIONS OF ID REGISTER DC BRIGHTNESS CONTROL REGISTER BRTDC5 BRTDC4 BRTDC3 BRTDC2 BRTDC1 BRTDC0
REV[2..0]
REGISTER 0x07 BRTDC7 BRTDC6
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT BRTDC[7..0] BIT FIELD DEFINITIONS = 256 steps of DC brightness levels FIGURE 34. DESCRIPTIONS OF DC BRIGHTNESS CONTROL REGISTER
DC Brightness Control Register (0x07)
The DC Brightness Control Register 0x07 allows users to have additional dimming flexibility by: 1. Effectively achieving 16-bits of dimming control when DC dimming is combined with PWM dimming 2. Achieving visual or audio noise free 8-bit DC dimming over potentially noisy PWM dimming. The bit assignment is shown in Figure 34. All of the bits in this Register can be read or write. Steps 0 to 255 represent the linear steps of current adjustment in DC on-the-fly. It can also be considered as the peak current factory calibration feature to account for various LED production batch variations, but external EEPROM settings storing and restoring are required. * An SMBus/I2C Write Byte cycle to Register 0x07 sets the brightness level in DC only. * An SMBus/I2C Read Byte cycle to Register 0x07 returns the current DC brightness level. * Default value for Register 0x07 is 0xFF.
Configuration Register (0x08)
The Configuration Register provides many extra functions that users can explore in order to optimize the driver performance at a given application. A DirectPWM bit allows Direct PWM where the output current follows the same input PWM signal.The FSW bit allows users to set the boost conversion switching frequency between 1.2MHz and 600kHz. The VSC bits allow users to set 3 levels of channel short-circuit thresholds or disable it. The bit assignment is shown in Figure 35. The default value for Register 0x08 is 0x1F.
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Output Channel Mask/Fault Readout Register (0x09)
This register can be read or write; the bit position corresponds to the channel. For example, Bit 0 corresponds to Ch0 and bit 5corresponds to Ch5 and so on. Writing data to this register, it enables the channels of interest. When reading data from this register, any disabled channel and any faulted out channel will read as 0. This allows the user to determine which channel is
REGISTER 0x08 RESERVE D RESERVE D CONFIGURATION REGISTER
faulty and optionally not enabling it in order to allow the rest of the system to continue to function. Additionally, a faulted out channel can be disabled and re-enabled in order to allow a retry for any faulty channel without having to power-down the other channels. The bit assignment is shown in Figure 36. The default for Register 0x09 is 0x3F.
BIT5 0 (W)
BIT4 1(W)
BIT3 1(W)
FSW
VSC1
VSC0
Bit 7 (R/W) Bit 6 (R/W) BIT ASSIGNMENT DirectPWM
Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT FIELD DEFINITIONS Forces the PWMI signal to directly control the current sources. Note that there is some synchronous delay between PWMI and current sources. These bits should always be written as 011 2 levels of Switching Frequencies (1 = 1,200kHz, 0 = 600kHz) 3 levels of Short-Circuit Thresholds (0 = disabled, 1 = 3.6V, 2 = 4.8V, 3 = 5.8V) FIGURE 35. DESCRIPTIONS OF CONFIGURATION REGISTER
BITS[5-3] FSW VSC[1..0]
REGISTER 0x09 Reserved Reserved
OUTPUT CHANNEL REGISTER CH5 CH4 CH3 CH2 CH1 CH0
Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W) BIT ASSIGNMENT CH[5..0] BIT FIELD DEFINITIONS CH5 = Channel 5, CH4 = Channel 4 and so on FIGURE 36. OUTPUT CHANNEL REGISTER
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REGISTER 0x0A PHASE SHIFT CONTROL REGISTER
EQUALPHASE PHASESHIFT6 PHASESHIFT5 PHASESHIFT4 PHASESHIFT3 PHASESHIFT2 PHASESHIFT1 PHASESHIFT0 Bit 7 (R/W) Bit 6 (R/W) Bit 5 (R/W) Bit 4 (R/W) Bit 3 (R/W) Bit 2 (R/W) Bit 1 (R/W) Bit 0 (R/W)
BIT ASSIGNMENT EqualPhase PhaseShift[6..0]
BIT FIELD DEFINITIONS Controls phase shift mode - When 0, phase shift is defined by PhaseShift<6:0>. When 1, phase shift is 360/N (where N is the number of channels enabled). 7-bit Phase shift setting - phase shift between each channel is PhaseShift<6:0>/(255*PWMFreq) In direct PWM modes, phase shift between each channel is PhaseShift<6:0>/12.8MHz FIGURE 37. DESCRIPTIONS OF PHASE SHIFT CONTROL REGISTER
Phase Shift Control Register (0x0A)
The Phase Shift Control register is used to set phase delay between each channels. When bit 7 is set high, the phase delay is set by the number of channels enabled and the PWM frequency. Refer to Figures 4 and 5, the delay time is defined by Equation 17:
t D1 = ( t FPWM N ) (EQ. 17)
Rearranging the terms without accounting for VD gives the boost ratio and duty cycle respectively as:
VO VI = 1 ( 1 - D ) D = ( VO - VI ) VO (EQ. 21) (EQ. 22)
Input Capacitor
Switching regulators require input capacitors to deliver peak charging current and to reduce the impedance of the input supply. This reduces interaction between the regulator and input supply, thereby improving system stability. The high switching frequency of the loop causes almost all ripple current to flow in the input capacitor, which must be rated accordingly. A capacitor with low internal series resistance should be chosen to minimize heating effects and improve system efficiency, such as X5R or X7R ceramic capacitors, which offer small size and a lower value of temperature and voltage coefficient compared to other ceramic capacitors. In Boost mode, input current flows continuously into the inductor; AC ripple component is only proportional to the rate of the inductor charging, thus, smaller value input capacitors may be used. It is recommended that an input capacitor of at least 10F be used. Ensure the voltage rating of the input capacitor is suitable to handle the full supply range.
where N is the number of channels enabled, and tFPWM is the period of the PWM cycle. When bit 7 is set low, the phase delay is set by bits 6 to 0 and the PWM frequency. Referencing Figure 24, the programmable delay time is defined by Equation 18:
t PD = ( PS < 6, 0 > xt FPWM ( 255 ) ) (EQ. 18)
where PS is an integer from 0 to 127, and tFPWM is the period of the PWM cycle. By default, all the register bits are set low, which sets zero delay between each channel. Note that the user should not program the register to give more than one period of the PWM cycle delay between the first and last enabled channels.
Components Selections
According to the inductor Voltage-Second Balance principle, the change of inductor current during the switching regulator On time is equal to the change of inductor current during the switching regulator Off time. Since the voltage across an inductor is:
V L = L x I L t (EQ. 19)
Inductor
The selection of the inductor should be based on its maximum current (ISAT) characteristics, power dissipation (DCR), EMI susceptibility (shielded vs unshielded), and size. Inductor type and value influence many key parameters, including ripple current, current limit, efficiency, transient performance and stability. The inductor's maximum current capability must be adequate enough to handle the peak current at the worst case condition. If an inductor core is chosen with too low a current rating, saturation in the core will cause the effective inductor value to fall, leading to an increase in peak to average current level, poor efficiency and
and IL @ On = IL @ Off, therefore:
( V I - 0 ) L x D x tS = ( VO - VD - VI ) L x ( 1 - D ) x tS (EQ. 20)
where D is the switching duty cycle defined by the turnon time over the switching period. VD is Schottky diode forward voltage that can be neglected for approximation.
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overheating in the core. The series resistance, DCR, within the inductor causes conduction loss and heat dissipation. A shielded inductor is usually more suitable for EMI susceptible applications, such as LED backlighting. The peak current can be derived from the voltage across the inductor during the Off period, as expressed in Equation 23:
IL pk = ( V O x I O ) ( 85% x V I ) + 1 2 [ V I x ( V O - V I ) ( L x V O x f SW ) ] (EQ. 23)
the best choice for output capacitors in small to medium sized LCD backlight applications due to their cost, form factor, and low ESR. A larger output capacitor will also ease the driver response during PWM dimming Off period due to the longer sample and hold effect of the output drooping. The driver does not need to boost harder in the next On period that minimizes transient current. The output capacitor is also needed for compensation, and, in general 2x4.7F/50V ceramic capacitors are suitable for notebook display backlight applications.
The choice of 85% is just an average term for the efficiency approximation. The first term is the average current, which is inversely proportional to the input voltage. The second term is the inductor current change, which is inversely proportional to L and fSW. As a result, for a given switching frequency and minimum input voltage on which the system operates, the inductor ISAT must be chosen carefully. At a given inductor size, usually the larger the inductance, the higher the series resistance because of the extra winding of the coil. Thus, the higher the inductance, the lower the peak current capability. The ISL97671 current limit should also have to be taken into account.
Schottky Diode
A high speed rectifier diode is necessary to prevent excessive voltage overshoot, especially in the boost configuration. Low forward voltage and reverse leakage current will minimize losses, making Schottky diodes the preferred choice. Although the Schottky diode turns on only during the boost switch Off period, it carries the same peak current as the inductor, and therefore, a suitable current rated Schottky diode must be used.
Applications
High Current Applications
Each channel of the ISL97671 can support up to 30mA. For applications that need higher current, multiple channels can be grouped to achieve the desirable current. For example, the cathode of the last LED can be connected to CH0 to CH2, this configuration can be treated as a single string with 90mA current driving capability.
VOUT
Output Capacitors
The output capacitor acts to smooth the output voltage and supplies load current directly during the conduction phase of the power switch. Output ripple voltage consists of the discharge of the output capacitor for ILPEAK during FET On and the voltage drop due to flowing through the ESR of the output capacitor. The ripple voltage can be shown as:
V CO = ( I O C O x D f S ) + ( ( I O x ESR ) (EQ. 24)
The conservation of charge principle in Equation 24 also brings up the fact that during the boost switch Off period, the output capacitor is charged with the inductor ripple current minus a relatively small output current in boost topology. As a result, the user needs to select an output capacitor with low ESR and enough input ripple current capability.
CH0 CH1 CH2
Output Ripple
VCo, can be reduced by increasing Co or fSW, or using small ESR capacitors. In general, Ceramic capacitors are
FIGURE 38. GROUPING MULTIPLE CHANNELS FOR HIGH CURRENT APPLICATIONS
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Multiple Drivers Operation
For large LCD panels where more than 6channels of LEDs are needed, multiple ISL97671s with each driver having its own supporting components can be controlled together with the common SMBus/I2C. While the ISL97671 does not have extra pins strappable slave address feature, but a separate EN signal can be applied to each driver for asynchronous operation. A trade-off of such scheme is that an exact faulty channel cannot be identified since both controllers have the same I2C slave address.
16-Bit Dimming
The SMBus/I2C controlled PWM and DC dimmings can be combined to effectively provide 16 bits of dimming capability, which can be valuable for automotive and avionics display applications.
SMBCLK SMBDAT EN
SMBCLK SMBDAT EN
SMBCLK SMBDAT EN
FIGURE 39. MULTIPLE DRIVERS OPERATION
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE 6/24/10 REVISION FN7631.0 Initial Release. CHANGE
Products
Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL97671 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 27
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Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 3/10
3.00 A B
4
0.10 M C A B 0.05 M C 20X 0.25
+0.05 -0.07
16X 0.50 6 PIN 1 INDEX AREA (C 0.40) 1
A
6 PIN 1 INDEX AREA 16
17
20
4.00 2.65
+0.10 -0.15
11 0.15 (4X) 10 7
+0.10 -0.15
6
A
TOP VIEW
VIEW "A-A"
1.65 20x 0.400.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C 0.9 0.10
C
SEATING PLANE 0.08 C (16 x 0.50) (2.65) (3.80) (20 x 0.25) C 0.2 REF 5
SIDE VIEW
(20 x 0.60) (1.65) (2.80)
0.00 MIN. 0.05 MAX.
DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature.
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